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Edge evaluation techniques for graphics hardware

Image Number 7 for United States Patent #8063903.

The edge evaluation technique, in accordance with one embodiment of the present technology, includes determining a number of edges of a given primitive to be evaluated. The technique also includes sequencing evaluation of a first edge by a first edge evaluation circuit and a second edge by a second edge evaluation circuit during a first clock cycle. The technique further includes sequencing evaluation of a third edge by the first edge evaluation circuit and a fourth edge by the second edge evaluation circuit during a second clock cycle if three or more edges are to be evaluated.

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