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Semiconductor IC incorporating a co-debugging function and test system










Image Number 5 for United States Patent #8055946.

A semiconductor IC capable of debugging two or more processors at the same time using a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.








 
 
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