Image Number 7 for United States Patent #8031092.
Methods and systems are described relating to dual-mode based digital background calibration of pipelined ADCs, for gain variations and device mismatches. Errors caused by gain insufficiency, nonlinearity, and capacitor mismatches are corrected by operating one ADC in two circuit configurations. These two modes are so arranged that their digital outputs differ in the presence of gain nonlinearity, gain insufficiency, and capacitor mismatches. The output difference is measured by randomly choosing one of the two operation modes at each sampling clock and digitally correlating the resulting digital output sequence. The measured output difference, which represents ADC errors, is used to remove the errors.