 |
|
 |
| |
Image Number 3 for United States Patent #7993992.
There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.
|
|
|
 |
|
 |
|
| |
Randomly Featured Patents |
|
