Resources Contact Us Home
Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns

Image Number 5 for United States Patent #7989335.

In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

  Recently Added Patents
Motion-compensated prediction of inter-layer residuals
Polymers derived from benzobis(silolothiophene) and their use as organic semiconductors
Multi user MIMO detection utilizing averaged spatial whitening
Owner-brokered knowledge sharing machine
Gaze tracking password input method and device utilizing the same
Digital-to-analog converter and performing method thereof
  Randomly Featured Patents
LED optical assembly
Feeding mechanism for granular material
Welded joint in segmented sheath for compressed gas insulated transmission lines
Semiconductor device having quasi-SOI structure
Cooperating slidable aluminum alloy members
Thiazoline carbamoyl-oximes
Method for increasing the weight gain and improving the feed utilization efficiency of livestock
Nucleation for improved flash erase characteristics
Secure socket apparatus
Active filter for a converter having a DC line