Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Logic circuit, address decoder circuit and semiconductor memory










Image Number 6 for United States Patent #7982505.

Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.








 
 
  Recently Added Patents
Control apparatus for autonomous operating vehicle
Illumination apparatus for microlithography projection system including polarization-modulating optical element
Systems and methods for mitigating spectral regrowth from non-linear systems
Nuclear reactor building and construction method thereof
Coding circuitry for difference-based data transformation
Image forming apparatus and method for making density correction in a low resolution image based on edge determination
Surfcraft fin
  Randomly Featured Patents
Soccer ball radio
Collapsible carton sleeve
Multiple drum winches
Drafting instrument
Biomass (woodfuel) cogeneration powerplant
Method of fabricating a safety harness
Imaging cylinder containing heat sensitive thiosulfate polymer and methods of use
Method of preventing abrasion at sliding portion of metal-product
Brake control device
Multiple input bit-line detection with phase stealing latch in a memory design