Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Logic circuit, address decoder circuit and semiconductor memory










Image Number 6 for United States Patent #7982505.

Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.








 
 
  Recently Added Patents
Method for forming contact hole
All-angle light emitting element having high heat dissipating efficiency
Dimmable LED light fixture having adjustable color temperature
Face recognition through face building from two or more partial face images from the same face
Cooking device and method of manufacture of the same
Lighting elements
Acoustic echo cancellation
  Randomly Featured Patents
Locomotive engine charge air cooling system and method for cooling the engine
Image displaying apparatus wherein selected stored image data is combined and the combined image data is displayed
Chair
Archery accessory adapter
Auxiliary port and outlet extender
Enzyme inhibitors
Whole body vibrator (II)
Auto-injector
Regulator circuit with multiple supply voltages
Process for producing a protected heat-mode recording material