Image Number 7 for United States Patent #7977232.
A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnections may be disposed in the stack of inter-layer insulators. The multi-level interconnections may extend in the device region. An electrode layer may be disposed over the stack of inter-layer insulators. The electrode layer may extend in the device region. The electrode layer may cover the multi-level interconnections. A cracking stopper groove may be disposed in the dicing region. The cracking stopper groove may be positioned outside the device region.
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