Resources Contact Us Home
Interleaving saturated lower half of data elements from two source registers of packed data

Image Number 14 for United States Patent #7966482.

An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

  Recently Added Patents
Semiconductor device with an amorphous semi-insulating layer, temperature sensor, and method of manufacturing a semiconductor device
Controller with screen
Preserving and handling native data in hybrid object trees
3D IC method and device
Motor drive component verification system and method
Down-drawable, chemically strengthened glass for cover plate
Light emitting device
  Randomly Featured Patents
Thermoplastic melting apparatus
Quenching reagents for solution phase synthesis
Multi-channel imager
Power supply
Hand-held food processor and blade assembly
Semiconductor device and method for manufacturing the same
Air purifier apparatus with an electrostatic filter
Copper liquor analyzer
Method of accessing a disk-like recording medium in a disk cartridge
Electric rotating machine and electromagnetic machine and apparatus