Resources Contact Us Home
Interleaving saturated lower half of data elements from two source registers of packed data

Image Number 14 for United States Patent #7966482.

An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

  Recently Added Patents
MEMS structure and method for making the same
Method and system for using personal devices for authentication and service access at service outlets
Method and system for simulating wireless networks
2,5-disubstituted piperidine orexin receptor antagonists
Dual work function recessed access device and methods of forming
Highly stable electrolytic water with reduced NMR half line width
  Randomly Featured Patents
Electric circuit apparatus of injection molding machine
Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication
Power amplifier
Combined vessel dissection and transection device and method
Plant pot
X-ray diffractometer having co-exiting stages optimized for single crystal and bulk diffraction
Persistent volume mount points
Apparatus for recording magneto-optic disks
Method of and apparatus for producing micro lens and micro lens
Implantable medical lead having passive lock mechanical body terminations