Resources Contact Us Home
Interleaving saturated lower half of data elements from two source registers of packed data

Image Number 12 for United States Patent #7966482.

An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

  Recently Added Patents
Programmable computer mouse
Data latch circuit and electronic device
Method and system for providing complete internet anywhere with partial server processing
Austenitic stainless steel welding wire and welding structure
Flavonoid dimers and methods of making and using such
Method and system for determining an optimal missile intercept approach direction for correct remote sensor-to-seeker handover
Image reading apparatus, image reading method and program
  Randomly Featured Patents
Backlighting method for an automotive trim panel
Insert for shoes
Baggage compartment, in particular an enclosed compartment for an aircraft cabin
Cleansing compositions
Optimizing power management in multicore virtual machine platforms by dynamically variable delay before switching processor cores into a low power state
Combined cooking and baking grill
Lead frame, method of manufacturing the same, and method of manufacturing a semiconductor device using the same
Multipurpose tool
Processes for the preparation of SGLT2 inhibitors
Microwave oven