Resources Contact Us Home
Interleaving saturated lower half of data elements from two source registers of packed data

Image Number 12 for United States Patent #7966482.

An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

  Recently Added Patents
Chromene compound
Polarity switching member of dot inversion system
Liquid crystal display device
Process for preparing red cocoa ingredients, red chocolate, and food products
Representations of compressed video
Sensor packages and method of packaging dies of differing sizes
  Randomly Featured Patents
PRO4989 polypeptides
Battery box
Memory element and memory device
Material handling pushback
PFC converter having two-level output voltage without voltage undershooting
Cup holder
System for neutralizing a concealed explosive within a container
Communication device with smart antenna using a quality-indication signal
Radiation image storage panel
Liquid ejection head and image forming apparatus