Resources Contact Us Home
Interleaving saturated lower half of data elements from two source registers of packed data

Image Number 12 for United States Patent #7966482.

An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

  Recently Added Patents
Modified binding proteins inhibiting the VEGF-A receptor interaction
Systems and methods for reducing narrow bandwidth interference contained in broad bandwidth signals
SONOS stack with split nitride memory layer
Portable computer display structures
Bundled flexible cable with water resistant structure
Three-dimensional shape data processing apparatus and three-dimensional shape data processing method
  Randomly Featured Patents
Clamping strips and locking channels
Ultrasound diagnosis apparatus and program
Multi-mode high efficiency linear power amplifier
Easy handling sleeve for small tools
Fishing swivel weed guard resonating system
Semiconductor cooling device and stack of semiconductor cooling devices
Apparatus and method for dispensing elongated items
Embossing system for embossing pre-formed marker elements
Multi-position, retractable leg rest for a wheelchair
Automatic mapping, monitoring, and control of computer room components