Resources Contact Us Home
Interleaving saturated lower half of data elements from two source registers of packed data

Image Number 12 for United States Patent #7966482.

An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

  Recently Added Patents
Electrical stimulation lead, system, and method
Systems and methods for detailed error reporting in data storage systems
Semiconductor device
System and method for dynamic quality-of-service-based billing in a peer-to-peer network
Method and composition for improving skin barrier function
Electrical conduit containing a fire-resisting thermoplastic composition
Data recording apparatus with recording control based on defect block and control method thereof
  Randomly Featured Patents
Quick drip coffeemaker with thermal carafe
Twin blower airhouse
Methods for making holographic data storage articles
Optical add/drop wavelength switch
Displaying film-originated video on high frame rate monitors without motions discontinuities
Guide wire assembly and method for catheter exchange
Methods for treating hydrocarbon recovery operations and industrial waters
Loading/unloading unit for card media
Method and device to process digital media streams
Optical pickup device and information recording/reproduction device