Resources Contact Us Home
Interleaving saturated lower half of data elements from two source registers of packed data

Image Number 12 for United States Patent #7966482.

An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

  Recently Added Patents
Battery terminal with current sensor
Switch redundancy in systems with dual-star backplanes
Placental tissue grafts
Illumination unit for a direct-view display
Method for processing an algae medium containing algae microorganisms to produce algal oil and by-products
Synchronization of communication equipment
Shower bench
  Randomly Featured Patents
Phase varying device for engine
Internal combustion engine oil pressure loss safety device
Methods and apparatus for network communications via a transparent security proxy
Medical catheter with grooved soft distal segment
Dielectric hat bracket for safety hats
Step-up DC/DC voltage converter with improved transient current capability
Combined loudspeaker and stand with subwoofer
Holder for cathode ray tube and fabrication method thereof
Method for drying resin-used electronic parts
Counter-balancing mechanism