Image Number 7 for United States Patent #7945740.
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (`CPUs`); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.
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