Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Methods of fabricating transistors having buried P-type layers coupled to the gate










Image Number 5 for United States Patent #7943972.

A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.








 
 
  Recently Added Patents
Printed flexible multilayer twisted-pair shielded high speed data cable
Image-forming device
Moving picture processing apparatus, moving picture processing method, and program
Motorcycle
Prioritized random access method
Method and apparatus for layering software agents in a distributed computing system
Petunia plant named `Balpelite`
  Randomly Featured Patents
Moving image coding apparatus, moving image decoding apparatus, moving image coding method and moving image decoding method
Method and apparatus for gaging the degree of lobulation of bodies such as threaded fasteners
Method and apparatus for automatic sheet cutting and stacking
Methods for analyte sensing and measurement
Binoculars capable of vibration reduction
High temperature cooling system and method
Multi-tier rotary grill
Method and apparatus for treating stenoses at bifurcated regions
Fan control module for a system unit
System apparatus and method for applying voice mail short codes in a broadcast message system