Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Methods of fabricating transistors having buried P-type layers coupled to the gate










Image Number 5 for United States Patent #7943972.

A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.








 
 
  Recently Added Patents
Diffuser evaporator of active substance
Disinfecting caps for medical male luer connectors
Floating cell and island with a floating macrophyte filter
System and method of conducting games of chance with enhanced payouts based on cash in amount
Combination enhanced therapy
Electronic card reader
Liquid crystal display and chip on film thereof
  Randomly Featured Patents
Selectively positionable weather vane and display for vertical post
Process for producing iron briquettes and/or cold iron sponge
Nucleic acids encoding receptor recognition factors and methods of use thereof
Method of producing a semiconductor dynamic sensor
Light amount adjusting apparatus and image pickup apparatus
Cytological sampling method and device
Sub-marine telephone cable
Buckle
Wide concentration range gas detection
Process for the preparation of 2,3-dichlorosulphonyl-acrylonitriles