Resources Contact Us Home
Methods of fabricating transistors having buried P-type layers coupled to the gate

Image Number 5 for United States Patent #7943972.

A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

  Recently Added Patents
Data consumption framework for semantic objects
Anti-infective derivatives, method for the production thereof, pharmaceutical compositions containing same and uses of said derivatives in treatment
Data output apparatus and data output method
Memory controller including a hardware compression and decompression engine for managing system memory and graphical operations
Methods, systems, and products for providing communications services
Light modulators and optical apparatuses including the same
Method for producing a flexible composite elastomeric polyurethane skin
  Randomly Featured Patents
Dual headset cradle
Chlorinating apparatus
Methods of selectively oxidizing semiconductor structures, and structures resulting therefrom
Stable pharmaceutical composition and methods of using same
Lignin based colloidal compositions
Method and system for utilizing reduced functionality processing channels in a GNSS receiver
Musical toy
Shared global word line magnetic random access memory
Overfolding device