Resources Contact Us Home
Methods of fabricating transistors having buried P-type layers coupled to the gate

Image Number 5 for United States Patent #7943972.

A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

  Recently Added Patents
Method for manufacturing and reoxidizing a TiN/Ta.sub.2O.sub.5/TiN capacitor
Local access to data while roaming with a mobile telephony device
Escalating data backup protection in response to a failure in a cluster of nodes
Apparatus for focus beam analysis of high power lasers
Sending targeted product offerings based on personal information
Photoelectric conversion module
Device with a floating head having a heater element
  Randomly Featured Patents
Process for generating ultra high purity H.sub.2 or O.sub.2
Automatic solid-phase microextraction sampling apparatus
Method of washing clothes using a washing machine
Method and apparatus for driving plasma display panel
Surface mount electrical connector with anti-wicking terminals
High density storage of ammonia
Zoom lens and photographing apparatus having the same
Reconfigurable artificial magnetic conductor
Device abstraction system and method for a distributed architecture heating, ventilation and air conditioning system