Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Methods of fabricating transistors having buried P-type layers coupled to the gate










Image Number 5 for United States Patent #7943972.

A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.








 
 
  Recently Added Patents
Regenerative power storage system mounted on DC electric railway car
Distylium plant named `PIIDIST-I`
Analogue-to-digital converter
Crystalline form of zofenopril calcium
Method and system for generating and displaying an interactive dynamic graph view of multiply connected objects
Off-loading of processing from a processor blade to storage blades based on processing activity, availability of cache, and other status indicators
System for targeted delivery of therapeutic agents
  Randomly Featured Patents
Combustion engine air supply system
Derivatization of proteins
High-speed logarithmic photo-detector
Heat exchanger with tank utilizing integral positioning guides
Method and apparatus for pressing seams open on sewing machines
Multimedia information and information inquiry download service
Casket having quickly interchangeable and adjustable interior
Roofing products including granules with reflective coating
Timing of and minimizing external influences on digital signals
Single pole type recording head with trailing side tapered edges