Resources Contact Us Home
Methods of fabricating transistors having buried P-type layers coupled to the gate

Image Number 5 for United States Patent #7943972.

A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

  Recently Added Patents
Method and apparatus for complementing an instrument panel by utilizing augmented reality
Storage system with LU-setting function
Multilayered material sheet and process for its preparation
Information processing apparatus, information processing method, and program
Poloxamer foamable pharmaceutical compositions with active agents and/or therapeutic cells and uses
Network based technique for obtaining operator identifier for mobile devices
  Randomly Featured Patents
Protection of nozzle structures in a liquid-ejection integrated circuit device
Apparatus for measuring fine particles in liquid
PCB design and method for providing vented blind vias
Fitting and pipe section for jetted bath heaters
Method for regulating the climate in a room
Rigid resealable label flap having a hinge
Raindrop detection wiper
Soybean cultivar S07-02JR409106
Doppler radar systems
Method of thinning semiconductor wafer of smaller diameter than thinning equipment was designed for