Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Methods of fabricating transistors having buried P-type layers coupled to the gate










Image Number 5 for United States Patent #7943972.

A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.








 
 
  Recently Added Patents
Display stand for a mobile tablet computer
N-phenyl-(homo)piperazinyl-benzenesulfonyl or benzenesulfonamide compounds suitable for treating disorders that respond to the modulation of the serotonin 5-HT.sub.6 receptor
Information display
Engine RPM control device
Extensible framework for client-based active network measurement
Real-time application of filters based on image attributes
Method for producing cathode active material for a lithium secondary battery
  Randomly Featured Patents
Method for impregnating a thermoplastic polymer
Linearly adjustable multi resistance ratio exercise apparatus
Non-flooding belt feeder
Transgenic animal model for degenerative diseases of cartilage
Socket coil-on-plug retainer
Semiconductor memory device and write method of the same
Method and continuous casting ingot mold for shaping continuous castings
Method of fabricating X-ray masks with reduced errors
Drill pipe protector
Portable gas burner with detachable reflector and base