Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Methods of fabricating transistors having buried P-type layers coupled to the gate










Image Number 5 for United States Patent #7943972.

A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.








 
 
  Recently Added Patents
Debugging using code analysis
Location-based method to specify ratio frequency spectrum rights
Memory device program window adjustment
Flexure with insulating layer isolating a portion of a metal substrate
Method and system for providing complete internet anywhere with partial server processing
Peptides useful in the treatment and/or care of skin, mucous membranes, scalp and/or hair and their use in cosmetic or pharmaceutical compositions
Surface modification
  Randomly Featured Patents
Luggage with pull handle
Treatment of Sjogren's syndrome by administration of TR18 polypeptides
Apparatus for assembling body panels
Process of measuring conductivity using a pH analyzer
Biheteroaryl metal complexes as bleach catalysts
Load cell assembly
Test gas leak detector
Water-resistant grease and water-resistant-grease-enclosed rolling bearing and hub
Crossbeam for a motor vehicle
Adjustable length handle for flat finishers