Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Split gate non-volatile memory cell with improved endurance and method therefor










Image Number 9 for United States Patent #7923328.

A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.








 
 
  Recently Added Patents
Light emitting device and light emitting device package
Satellite fleet deployment
Simplifying lexicon creation in hybrid duplicate detection and inductive classifier systems
Block copolymer nanoparticle compositions
Liquid dispensing apparatus
Motion estimation for a video transcoder
Stable light source device
  Randomly Featured Patents
Motor vehicle lighting system including a sealed lens member as part thereof
Materials for organic electroluminescent devices containing substituted 10-benzo[c]phenanthrenes
TENS device with electronic pain intensity scale
Spring and retainer assembly and spring delashed steering shafts
Faucet handle
Method for preparing hydrocarbon mixture solvent
Bristled septic filter
Benzoyl derivatives, process for their preparation and their use as herbicides and plant growth regulators
Positive-displacement, fluid machine
Method of testing an evaluation circuit