Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Systems and methods for reduced complexity LDPC decoding










Image Number 2 for United States Patent #7895500.

Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the standard sum-product algorithm (SPA), and can reduce the approximation error of min-sum algorithm (MSA) and have almost the same performance as sum-product algorithm (SPA) under both floating precision operation and fixed-point operation.








 
 
  Recently Added Patents
Selective high frequency spinal cord modulation for inhibiting pain with reduced side effects, and associated systems and methods
Pallet
Workflow-enabled client
Method and system for video parameter analysis and transmission
Method for media access controlling and system and method for channel time reservation in distributed wireless personal area network
Image display device and capsule endoscope system
Organic light-emitting display with black matrix
  Randomly Featured Patents
CMOS voltage reference circuit
Method for preparing a porous inorganic coating on a porous support using certain pore formers
Beverage filter cartridge
Optical combiner device
System and an apparatus for confining a pet within a preselected area
Quantitative analyzing method and quantitative analyzer using sensor
Damped hinge mounting mechanism
3-point/5-point fastener, 3-point/5-point bit
Optical fiber lighting apparatus
Switch structure, electronic component part installing structure, and electronic musical instrument including the same