Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Flash memory gate structure for widened lithography window










Image Number 15 for United States Patent #7888729.

A first portion of a semiconductor substrate belonging to a flash memory device region is recessed to a recess depth to form a recessed region, while a second portion of the semiconductor substrate belonging to a logic device region is protected with a masking layer. A first gate dielectric layer and a first gate conductor layer formed within the recessed region such that the first gate conductive layer is substantially coplanar with the top surfaces of the shallow trench isolation structures. A second gate dielectric layer, a second gate conductor layer, and a gate cap hard mask layer, each having a planar top surface, is subsequently patterned. The pattern of the gate structure in the flash memory device region is transferred into the first gate conductor layer and the first gate dielectric layer to form a floating gate and a first gate dielectric, respectively.








 
 
  Recently Added Patents
Buckle
Portion of a display panel with an unhappy facial expression icon
Apparatus and method for information processing, program, and recording medium
Systems and methods for restoring images
Image sensor pixels with junction gate photodiodes
Wireless communication apparatus, a method of wireless communication, and a program for wireless communication
Switchgear operating apparatus and three-phase switchgear
  Randomly Featured Patents
Method of exchanging communicated signals between a remote base site and a central site in a communication system
Magneto-optical switching backplane for processor interconnection
Parabolic heater
Vibration motors
Plastic optical fiber with a lens portion, optical fiber connector, and connecting structures and methods between optical fibers and between optical fiber and light emitting/receiving device
Digital data communication system using video telephony
Elastic store slip circuit apparatus for preventing read and write operations interference
Guy-wire guard assembly and fastening systems therefor
Use of E-field sensors for situation awareness/collision avoidance
Memory cell storage node length