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Chip stacked structure and the forming method

Image Number 8 for United States Patent #7888172.

A chip package structure is provided, includes a chip that having a plurality of pads and an adhesive layer on the back side; an encapsulated structure is covered around the four sides of the chip to expose the pads, and the through holes is formed within the encapsulated structure; a patterned first protective layer is formed on the portion surface of encapsulated structure, the portion of active surface of the chips, and the pads of the chip and the through holes are to be exposed; a metal layer is formed on the portion surface of the patterned first protective layer and formed to electrically connect the pads and to fill with the through holes; the patterned second protective layer is formed on the patterned first protective layer and the portion of metal layer, and the portion surface of metal layer is to be exposed; a patterned UBM layer is formed on the exposed surface of the metal layer and the portion surface of the patterned second protective layer; and the conductive elements is formed on the patterned UBM layer and electrically connect to the metal layer.

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