Image Number 4 for United States Patent #7858500.
A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO.sub.2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
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