Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Failsafe and tolerant driver architecture and method










Image Number 3 for United States Patent #7834653.

A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.








 
 
  Recently Added Patents
Categorizing bit errors of solid-state, non-volatile memory
Network client validation of network management frames
Antenna module and wireless communication apparatus
Vehicle control system
Method and system for migrating object update messages through synchronous data propagation
Predictive time entry for workforce management systems
Image forming apparatus
  Randomly Featured Patents
System and process for removing a background pattern from a binary image
Hand-held vacuum cleaner
Reproducible molding die having a removable cleaning layer
Image forming apparatus and image forming method
Portable tube-bending machine
Detonator primer capsule
Lubrication system having a gasket with integrated lubrication channel
Self drilling blind rivet
Impeller for a cooling fan
Soft tissue achieved by applying a solid hydrophilic lotion