Resources Contact Us Home
Failsafe and tolerant driver architecture and method

Image Number 3 for United States Patent #7834653.

A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.

  Recently Added Patents
Pre-colored methodology of multiple patterning
Sending targeted product offerings based on personal information
Phosphor, light emitting apparatus, and liquid crystal display apparatus using the same
Image capturing apparatus, control method thereof, and program
Generating a funding and investment strategy associated with an underfunded pension plan
Method and apparatus for providing seamless call handoff between networks that use dissimilar transmission methods
  Randomly Featured Patents
Device for maintaining the crimping of textile fibers or filaments during subsequent setting
Timepiece operated by solar cells
Ophthalmological measuring device
Utility lighter
Side-loading dish and tray cart
Scoop device
Implant vial
Photoprinter with self-locating roll spreader
Constant settling time automatic gain control circuits
Method of forming polycrystalline silicon layer and atomic layer deposition apparatus used for the same