Resources Contact Us Home
Failsafe and tolerant driver architecture and method

Image Number 3 for United States Patent #7834653.

A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.

  Recently Added Patents
Device and method for processing input data of protective relay
System and method for managing investment funds
Catalysts and process for producing aldehydes
Motilin-like peptide compound having transmucosal absorbability imparted thereto
Fan guide
Technology for managing traffic via dual homed connections in communication networks
  Randomly Featured Patents
System and method for automated filament testing of gas discharge lamps
Exercise apparatus for strengthening abdominal muscles
Corrector ring driving device of microscopic objective lens provided with corrector ring
Method for implementing dynamic pseudorandom keyboard remapping
Ceanothus plant named `FIT02`
Bubble generation in condensation wells for cooling high density integrated circuit chips
System, method and program for computer graphics rendering
Vegetable protein meat analog
Method for separating plastics-containing mixture