Resources Contact Us Home
Failsafe and tolerant driver architecture and method

Image Number 3 for United States Patent #7834653.

A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.

  Recently Added Patents
Support member, rotation device comprising such a support and rolling bearing assembly including such a detection device
Electrical stimulation lead, system, and method
Image-monitoring method for electroporation treatment and as associated image-monitoring appliance
Process for producing polyphenylene ether composition
Control unit of a ride level control system, and ride level control system
Linear book scanner
Pressure-sensitive adhesive composition having an improved release behavior
  Randomly Featured Patents
Rear suspension system for motorcycles
Eye shield sleeping device
High accuracy, high integrity scene mapped navigation
Quick coupler retention clip and method
Apparatus and method for medical procedures within a spine
Sheath flow forming device and sample analyzer provided with same
Image-forming machine having a cover member for covering part of an image bearing member
System for cell-based screening
Current-limiting fuse and housing arrangement
Machine guard safety gauge/Guardchek .TM.