Image Number 11 for United States Patent #7793844.
The invention provides a memory device (10) operable to receive an input signal and to generate a corresponding data bearing output signal in response, the device including a series of circuit stages (200) operable to be triggered by the input signal at a first stage of the series (stage 1) thereby causing a sequential triggering of stages along the series to a last stage of the series to generate the output signal, the data represented in time durations taken for each stage in the series to trigger a subsequent stage in the series. Sequential triggering of the stages generates a data bearing output signal for output from the device (10). The device (10, 800) can be modified to repetitively output the data in response to the input signal. Moreover, the device (900, 940) can be adapted to provide a delay before repeating the data, thereby coping with contention when several of the devices (900, 940) are operating within range of one another.
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