Resources Contact Us Home
Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle

Image Number 5 for United States Patent #7788469.

A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.

  Recently Added Patents
Centralized behavioral information system
Differentiated PSIP table update interval technology
Landscape post for solar and other light fixtures
Image forming apparatus and control method therefor
Storage device having clock adjustment circuitry with firmware-based predictive correction
Display stand for a mobile tablet computer
Radio frequency splitter
  Randomly Featured Patents
Adhesively secured pump fastener system
Engineering plastic composition and an article made of the same
Charging device, image forming apparatus and detachably mountable process cartridge having a constant voltage power source feature
Two part connector housings in strip form
Nonoral preparation having three-layer structure
Capacitor structure
Encapsulated fragrance chemicals
Thrust bearing for down-hole tool
Coolant control unit and cooled electronics system employing the same
Shortcut key manager and method for managing shortcut key assignment