Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle










Image Number 5 for United States Patent #7788469.

A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.








 
 
  Recently Added Patents
System for controlled release of an active principle and method for preparation
System and method for calibrating display device using transfer functions
Light emitting diode package and method of fabricating the same
Analog to digital converter with increased sub-range resolution
System and method for redundant array copy removal in a pointer-free language
Lacrosse head
Retransmission control method, base station and mobile station
  Randomly Featured Patents
Crushable hat
Controlling pulses in a laser texturing tool
Antiperspirant solution containing a mixture of substantially volatile and substantially non-volatile siloxane liquids
Ink cartridge venting
Intermediate molecular weight fluorine containing polymide and method for preparation
Semiconductor memory device
Electrical connection system that absorbs multi-connector positional mating tolerance variation
Integrated cascade refrigeration system
Image pickup apparatus having an exposure control circuit
Swim training apparatus