Resources Contact Us Home
Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle

Image Number 5 for United States Patent #7788469.

A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.

  Recently Added Patents
Circuit arrangement for a piezo transformer, and method therefor
Synergistic preparations based on mixtures of glycerol ether with aromatic alcohol for controlling mycobacteria
Tracking data eye operating margin for steady state adaptation
Malicious attack detection and analysis
Stage drive method and stage unit, exposure apparatus, and device manufacturing method
Electronic document reading devices
  Randomly Featured Patents
Implement with horizontal linkage depth control
Low pH Acidic Compositions
Database structure for a consumer reporting agency
Turbine exhaust catalyst
Electrolytic cell
Permanent magnetic power cell system for treating fuel lines for more efficient combustion and less pollution
Method for restricting total code volume in data-compression
Scan path system and an integrated circuit device using the same
Extended E matrix integrated magnetics (MIM) core
Plasma display device