Resources Contact Us Home
Analog reference voltage generator, method thereof, analog-to-digital converter including the same, and image sensor including the same

Image Number 16 for United States Patent #7755531.

An analog reference voltage generator for generating a monotonously increasing or decreasing analog reference voltage includes a plurality of dump cells in front of an operational amplifier and controls the dump cells using a plurality of clock signals, respectively, which do not overlap each other in time, thereby increasing a ramping speed. The analog reference voltage generator including the plurality of dump cells controls the generation of an analog reference voltage using the plurality of clock signals obtained by dividing a master clock signal, thereby preventing the voltage level of the reference signal from decreasing due to an increase of the load.

  Recently Added Patents
Driving apparatus having an optical sensor and a thermal sensor for thermal and aging compensation of backlight module and driving method of backlight module
Support member, rotation device comprising such a support and rolling bearing assembly including such a detection device
Toothbrush holder
Compositions and methods for producing isoprene
Cryptographically generated addresses using backward key chain for secure route optimization in mobile internet protocol
Battery comprising circuitry for charge and discharge control, and method of operating a battery
Reconstruction of deforming surfaces by canceling ambient occlusion and refining 3-D shape
  Randomly Featured Patents
Using application side truetype or other outline fonts to create specialty imaging fonts on digital front-end
Transmitter frequency peaking for optical fiber channels
Semi-modular pinrack seal
Electronic flight instrument displays
Method for assembling boot components to a chassis of a sports article and the boot/chassis thus assembled
Polymer compositions
Overhead luggage compartment, especially for passenger aircraft
Printing device
Semiconductor memory device with address transition detector