Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Dual gate structure for imagers and method of formation










Image Number 3 for United States Patent #7635624.

A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are produced, a silicide layer is provided over conductive layers, reducing resistance. The device can be an imager in which pixels in an array includes a capacitor and readout circuitry with NMOS transistors. Periphery circuitry around the array can include PMOS transistors. Because the silicide layer is formed after the conductive layers, it is not exposed to high temperatures and, therefore, migration and cross-contamination of dopants is reduced.








 
 
  Recently Added Patents
Organizer
Semiconductor element-embedded wiring substrate
Behavioral fingerprint based authentication
Composition for enhancing memory and mitigating neurodegeneration and method thereof
Systems and methods for advertising on content-screened web pages
Secure mobile ad hoc network
Method for manufacturing thin film transistor and method for manufacturing display device
  Randomly Featured Patents
X-Wing aircraft circulation control
Low-phosphate machine dishwashing detergents
Resonance driver
Extraction methods for preparing thromboplastin reagents
Method and apparatus for high denier hollow spiral fiber
Face shield
Ink jet recording process
Rechargeable battery
Apparatus for the preparation of packaging blanks by severing from a continuous web
Vehicle seat or similar article