Resources Contact Us Home
Dual gate structure for imagers and method of formation

Image Number 3 for United States Patent #7635624.

A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are produced, a silicide layer is provided over conductive layers, reducing resistance. The device can be an imager in which pixels in an array includes a capacitor and readout circuitry with NMOS transistors. Periphery circuitry around the array can include PMOS transistors. Because the silicide layer is formed after the conductive layers, it is not exposed to high temperatures and, therefore, migration and cross-contamination of dopants is reduced.

  Recently Added Patents
Large carrying case
Reuse of static image data from prior image frames to reduce rasterization requirements
Polynucleotide capture materials, and methods of using same
Curable sublimation marking material and sublimation transfer process using same
Device and method including a soldering process
Linerless labels
Multipoint photonic doppler velocimetry using optical lens elements
  Randomly Featured Patents
Disk gripper for use with a disk polisher
Method of impact printing with electrostatic or magnetic powder
Quick clamp and release vise
Regenerated cellulose membrane and processes for preparation thereof
Phase locked loop circuit with an unlock detection circuit and a switch
Magnetic shunting pads for optimizing target erosion in sputtering processes
Kissing shield game and method of use thereof
Generic external portable cooling device for computers
CO.sub.2 food freezer