Resources Contact Us Home
Dual gate structure for imagers and method of formation

Image Number 3 for United States Patent #7635624.

A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are produced, a silicide layer is provided over conductive layers, reducing resistance. The device can be an imager in which pixels in an array includes a capacitor and readout circuitry with NMOS transistors. Periphery circuitry around the array can include PMOS transistors. Because the silicide layer is formed after the conductive layers, it is not exposed to high temperatures and, therefore, migration and cross-contamination of dopants is reduced.

  Recently Added Patents
PVD coated tool
Systems and methods for adaptive blind mode equalization
Reducing energy and increasing speed by an instruction substituting subsequent instructions with specific function instruction
Liquid crystal shutter glasses
Systems and methods for parameter adaptation
Voltage level shift circuits and methods
Method and device for processing broadcast packets/multicast control messages
  Randomly Featured Patents
Fish scaler
Water-based coating compositions
Dual element filament mower
Electric power steering system
Methodology of using raman imaging microscopy for evaluating drug action within living cells
Face recognition through face building from two or more partial face images from the same face
Apparatus for supplying a resin material to an injection molding machine
Hydrogenation process using supported nickel catalyst
Patient monitor with user interface