Image Number 5 for United States Patent #7613905.
A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a critical functional unit. Each critical functional unit supplies its output to a pipeline register. A comparator and multiplexer select a register input for each functional unit or the output of a corresponding pipeline register dependent. In the preferred embodiment, each critical functional unit has a throughput delay time longer than the average of throughput delay times of all functional units.
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