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Image Number 5 for United States Patent #7606941.
A receiving FIFO device can prevent a PCI bus from being occupied unnecessarily to enhance the performance of a whole system. An input control part checks in a third comparing part whether or not a received packet written in a memory part is an error packet on the basis of acknowledge information contained in a trailer part of the received packet. If the received packet is the error packet, the input control part supplies a signal EMPTY being HIGH to an output control device and cancels the received packet, thereby preventing the error packet from being transferred to a receiving DMA device. Furthermore, the input control part checks in a second comparing part whether or not the received packet written in the memory part belongs to a predetermined type of packet on the basis of tcode information contained in the first quadret of a header part of the received packet. Only if the received packet belongs to the predetermined type of packet, the input control part cancels the received packet for a predetermined type of error.
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