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Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses










Image Number 6 for United States Patent #7582494.

A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or more active regions, wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.








 
 
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