Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Field effect transistor having a stressed dielectric layer based on an enhanced device topography










Image Number 8 for United States Patent #7563731.

By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.








 
 
  Recently Added Patents
Device for producing a connection grid with an integrated fuse
Regulating a supply voltage provided to a load circuit
Stable pharmaceutical composition and methods of using same
Combined high and low frequency stimulation therapy
Touch-sensitive device and communication device
Storage basket with lid
Charged particle beam apparatus
  Randomly Featured Patents
Shaft driven, flexible intravascular recanalization catheter
Spline and splinting board combination
External coating composition for toaster pastries and other pastry products
Rapid-separation mounting arrangement for rollers of a calendering machine
Clamshell retail package for transponder
Lens system with frontal aperture stop
Injectable multi-phase emulsions
Input gain adjusting apparatus and method
Anti-theft device for automobile vehicles
Coating for inhibiting stain formation in floor covering