Resources Contact Us Home
Field effect transistor having a stressed dielectric layer based on an enhanced device topography

Image Number 8 for United States Patent #7563731.

By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

  Recently Added Patents
Method and apparatus for storing email messages
Routing of data including multimedia between electronic devices
Process for producing dipeptides or dipeptide derivatives
Optoelectronic semiconductor chip comprising a reflective layer
Toilet bowl
Basket for a dishwasher
Integrated circuit packaging system with interconnects and method of manufacture thereof
  Randomly Featured Patents
Method for forming an interconnect structure
Shaped pintle wire for paper machine clothing
Binder composition for positive electrodes
Parking brake device in combination with a shift lever for use in a vehicle
Methods and uses of antibodies in the purification of interferon
Display label for an absorbent article
Trans-thermoelectric device
System and method for fitness evaluation for optimization in document assembly
Wire bonding process and wire bond structure
Method and system for controlling refresh to avoid memory cell data losses