Resources Contact Us Home
Field effect transistor having a stressed dielectric layer based on an enhanced device topography

Image Number 8 for United States Patent #7563731.

By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

  Recently Added Patents
Electrical converter with variable capacitor
Presenting a link to a user
Computer network running a distributed application
Video editing apparatus
Method and apparatus for an active low power mode of a portable computing device
Crystalline form of (R)-7-chloro-N-(quinuclidin-3-yl)benzo[b]thiophene-2-carboxamide hydrochloride monohydrate
  Randomly Featured Patents
Method and apparatus for reducing electrical power consumption in a machine monitor
Method, apparatus, and product for automatic generation of lexical features for speech recognition systems
Method of making grinding stones
Catalyst for polymerization and copolymerization of olefins
Method and apparatus for applying material to selected areas of a moving part
CMOS image sensors having pixel arrays with uniform light sensitivity
Method for treating web, treatment tank, continuous electroplating apparatus, and method for producing plating film-coated plastic film
Catalyst for purification of aromatic acids
Method of reducing the residual unsaturated monomer content of an aqueous dispersion of a saturated polymer
System and method for measuring stress during processing of an optical fiber