Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Field effect transistor having a stressed dielectric layer based on an enhanced device topography










Image Number 8 for United States Patent #7563731.

By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.








 
 
  Recently Added Patents
Interest point detection
Atomic oscillator and manufacturing method
High density molecular memory storage with read and write capabilities
Circuitry for measuring and compensating phase and amplitude differences in NDT/NDI operation
Multistable electromagnetic actuators
Control method and allocation structure for flash memory device
Use of emerging non-volatile memory elements with flash memory
  Randomly Featured Patents
Charging generator
Programmable device for diffusing olfactory peaks
Patient transporting dolly
Apparatus for making high strength open bottom packaging tray
High quality, continuous throughput, tissue processing
Method and apparatus for testing flammability properties of cellular plastics
Antibody that specifically binds to Candida kefyr Cytosine deaminase
Channel members
Apparatus for and method of embedding and extracting digital information and medium having program for carrying out the method recorded thereon
Cooling ring for use in manufacturing of fiberglass wool