Resources Contact Us Home
Field effect transistor having a stressed dielectric layer based on an enhanced device topography

Image Number 8 for United States Patent #7563731.

By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

  Recently Added Patents
Method and system for leveraging the power of one's social-network in an online marketplace
Wafer level package and fabrication method
Apparatus and method for multiplying frequency of a clock signal
Wireless communication system and wireless communication method
Data processing system, data processing method, and image forming apparatus
Image processing apparatus
Integrated analyses of breast and colorectal cancers
  Randomly Featured Patents
Front face of headgear for respiratory mask
Differential assembly with cover gasket having integral magnet
Planar high temperature superconductor filters with backside coupling
Power amplifier
Rotary mower spindle assembly
Handle for a sanitary fitting
Porous ceramic structure
Panel connecting arrangements
Security gate apparatus
Protective garment for the hip