Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Field effect transistor having a stressed dielectric layer based on an enhanced device topography










Image Number 8 for United States Patent #7563731.

By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.








 
 
  Recently Added Patents
Heat shield and laminated glass
Diagnostic data interchange
Polymers
Methods and systems for determining the reliability of transaction
Apparatus for electrographic printing or copying
Channel marking for chip mark overflow and calibration errors
Cover opening and closing unit and image forming apparatus including the same
  Randomly Featured Patents
Deployable structures and methods for assembling same
Method and system for executing a power-cutoff-specific process within a specific processor of a multiprocessor system
Control circuit for tap-switching power supplies and multi-tap transformers
Apparatus and method for displaying map
Protected flow meter rotor bearing
Charge pump current compensation for phase-locked loop frequency synthesizer systems
Binocular ophthalmoscope
Latchless surgical clip
Sport tights
Multitubular once-through boiler