Resources Contact Us Home
Attribute cache memory

Image Number 8 for United States Patent #7539030.

A memory system according to one embodiment includes a plurality of content addressable word decoders, and memory cells associated with each of the word decoders. A memory system according to another embodiment includes a word decoder storing an identifier which is a subset of a memory address, the word decoder being responsive to a match of the identifier and an incoming subset of the memory address. A memory system according to yet another embodiment includes a word decoder having more than sixteen address line inputs. A memory system according to a further embodiment includes a word decoder array having fewer word decoders than combinations of memory addresses. Methods are also provided.

  Recently Added Patents
Elastic polypropylene-based film compositions
Method and system for dynamically representing distributed information
Case for electronic device
Efficient implementation of hash algorithm on a processor
Sample chamber for laser ablation inductively coupled plasma mass spectroscopy
Silicone hydrogel, lens for eye and contact lens
Disk drive with a subset of sectors with reduced write-to-read gap
  Randomly Featured Patents
Alkane rejection in C.sub.4 etherification and isomerization process
Methanol automotive fuel
Class B driver
Vibrating and sonic device for toy gun
Liquid crystal display with integrated resistive touch sensor
Tiltable patient positioning table
Drum brake assembly and shoe hold-down and retraction spring therefor
Knock-down lamp shade
Process for the continuous partial crystallization and the separation of a liquid mixture
Fiber optic transceiver module release mechanism