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Image Number 3 for United States Patent #7484135.
A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a clock input terminal of the circuit block; a third signal path for guiding a test output signal from a output terminal of the circuit block to a pad via a dummy latch; and a fourth signal path for guiding the test output signal from the output terminal of the circuit block, to another pad. A dummy latch latches the test output signal at substantially a same speed as an operational latch during a normal operation. The third signal path has a wiring delay time from the output terminal to the dummy latch that is substantially equal to a wiring delay time from the output terminal to the operational latch.
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