Image Number 9 for United States Patent #7453742.
A semiconductor integrated circuit device includes a charge transfer transistor provided between a bit line and a sense amplifier, and a bit line clamp voltage generating circuit which generates bit line clamp voltage to be applied to the gate of the charge transfer transistor. The bit line clamp voltage generating circuit includes a current mirror circuit, a resistive dividing circuit provided between the input stage of the current mirror circuit and a reference potential node, a potential setting circuit provided between the output node of the resistive dividing circuit and the output stage of the current mirror circuit, and an operational amplifier which compares potential of the input stage of the current mirror circuit with reference potential to control the current mirror circuit. The operational amplifier is configured by transistors other than intrinsic transistors. The bit line clamp voltage is derived from the output stage of the current mirror circuit.
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