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Image Number 10 for United States Patent #7420535.

A display capable of suppressing reduction of a scanning property is provided. This display comprises a shift register circuit formed by connecting a plurality of first circuit parts each including a first conductivity type first transistor connected to a first potential and turned on in response to a clock signal, a first conductivity type second transistor connected to a second potential and a first conductivity type third transistor, connected between the gate of the first transistor and the second potential, having two gate electrodes electrically connected with each other.








 
 
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