Resources Contact Us Home
Substrate backgate for trigate FET

Image Number 13 for United States Patent #7411252.

Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.

  Recently Added Patents
Scalable packet processing systems and methods
Transmission device
Light-source control device, light-source control method, image reading device, and image forming apparatus
Fusing apparatus and image forming apparatus provided with the same, and heating apparatus
Compound semiconductor device and manufacturing method therefor
Method for producing vinyl acetate monomer
Embedded bonding pad for image sensors
  Randomly Featured Patents
Apparatus and method for positioning textile articles
Cigarette paper pack
Personal respirator backpack apparatus
IC testing apparatus
Portable carpet binder
Process for the manufacture of a ballistic-resistant moulded article
Circuit interrupter with improved welded contact interlock
Biological control of insects
Method for the production of a three-dimensional circuit arrangement
Method and apparatus for in situ anneal during ion implant