Image Number 17 for United States Patent #7372105.
A semiconductor device in which by fixing a well at a predetermined potential via a contact within a memory cell, latch-up immunity is improved without accompanying increase in the area of the memory cell, and of which manufacture is facilitated, and a manufacturing method thereof. In a semiconductor device including MOS transistors each having an N-type impurity region 110 formed in a P-well 101 provided in a silicon substrate 100 thereof and including a GND contact 130 for supplying a GND potential to the P-well 101, a portion of an impurity region 110 is etched and removed. Then, a P-type diffusion layer 131 for power supply is formed in the etched and removed region in the silicon substrate. Power supply to the P-well 101 is then performed via the GND contact 130 connected to the power supply diffusion layer 131.