Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Method of fabricating recess channel array transistor










Image Number 2 for United States Patent #7361537.

A method of fabricating a recess channel array transistor is disclosed. An impurity region is formed in a semiconductor substrate. Then, a polysilicon layer is formed on the semiconductor substrate, both of which are then etched to form a trench that defines an active region. By filling the trench with an insulating material, a STI and an interlayer insulating layer are formed. A patterned mask layer is formed to be used for etching the polysilicon layer and the interlayer insulating layer, thereby forming an opening that defines a contact pad. A Spacer is formed along a sidewall of the contact pad. Using the mask layer and the spacer, the semiconductor substrate is etched to thereby form a recess channel trench. Thereafter, a gate insulating layer and a gate conductive layer are formed. A nitride layer is formed on the resultant structure, and chemical mechanical polishing is performed to isolate the nodes.








 
 
  Recently Added Patents
Method and apparatus for internet on-line insurance policy service
Determining phase-specific parameters of a physiological variable
Methods of enhancing diabetes resolution
Weight-balanced polygonal mirror, light scanning unit using the polygonal mirror, and image forming apparatus
Probiotic Bifidobacterium strains
Constant low-flow air source control system and method
Systems and methods for processing telephone calls
  Randomly Featured Patents
Methods and compositions for controlling efficacy of RNA silencing
Desk
Video over IP network transmission system
Method for transitioning control of a peripheral device from a first device driver to a second device driver during operating system initialization
Luminescent analog-display device driven in response to two out of phase timing pulses
Domestic container with handle attached by gluing
Modification of pertussis toxin
Device for developing electrostatic latent image
Minimizing circulating current using time-aligned data
Method for wet processing of a semiconductor substrate