Image Number 3 for United States Patent #7332390.
A semiconductor memory device and fabrication method thereof. In a semiconductor memory device, each memory cell comprises a deep trench and a capacitor disposed on the lower portion thereof. A collar oxide layer having a first second sidewalls is disposed on the deep trench. The top of the first sidewall is at the same height as the surface of the semiconductor substrate. The top of the second sidewall is substantially equal to the top of the capacitor. The memory cell further comprises a buried conductor layer disposed on the second sidewall and the capacitor and a buried strap adjoining the buried conductive layer, and a transistor disposed on the surface of the semiconductor substrate and electrically connected to the capacitor through the buried strap and the buried conductive layer.