Image Number 12 for United States Patent #7268592.
An input/output buffer that protects a circuit from voltage signals provided from an external device. The input/output buffer includes a reference power generation circuit connected to a high voltage power supply and a low voltage power supply to convert the voltage of an external voltage signal and generate reference power. The reference power generation circuit has a protection circuit including a plurality of MOS transistors for decreasing the voltage of the external voltage signal to a predetermined voltage when the input/output buffer is not supplied with the voltage of the high voltage power supply. Each of the MOS transistors has a back gate connected to a predetermined node at which the voltage is less than the voltage of the high voltage power supply and greater than the voltage of the low voltage power supply.