Resources Contact Us Home
Multi-stage maximum likelihood target estimator

Image Number 3 for United States Patent #7266042.

A multi-stage maximum likelihood target estimator for use with radar and sonar systems is provided. The estimator is a software implemented algorithm having four computational stages. The first stage provides angle smoothing for data endpoints thereby reducing angle errors associated with tie-down times. The second stage performs a coarse grid search to obtain the initial approximate target state to be used as a starting point for stages 3 and 4. The third stage is an endpoint Gauss-Newton type maximum likelihood target estimate which determines target range along two time lines. The final refinement of the target state is obtained by the fourth stage which is a Cartesian coordinate maximum likelihood target estimate. The four-stage processing allows the use of target historic data while reducing processing time and computation power requirement.

  Recently Added Patents
Multi display device and method of controlling the same
Digital fine delay processing
Resonant oscillator with start up and shut down circuitry
Single mode optical fiber with improved bend performance
Semiconductor device and method for fabricating the same
Generating and using checkpoints in a virtual computer system
  Randomly Featured Patents
Method for global routing of electronic messages by encoding an originator's indica with identification of a corresponding service provider from stored database in a gateway control center
Redundant engine starting system
Fused heterocyclic compounds and analogs thereof, modulators of nuclear hormone receptor function
Polyester resin exhibiting optical anisotropy in molten state containing minor amounts of 6-oxy-2-naphthoyl units
Method of forming an electrode casing for an alkaline electrochemical cell with reduced gassing
Compact stacker for notes of various widths
Compounds obtained from salvia species having antiviral Activity
Methods for the treatment of cognitive disorders
Semiconductor memory device
Method and apparatus for testing operational amplifier leakage current