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Nanoscale latch-array processing engines

Image Number 12 for United States Patent #7227379.

One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be defined as sequences of one or more inputs to one or more of the nanowire data bus and nanoscale control lines. In various latch-array embodiments of the present invention, information can be transferred from one nanoscale latch to another nanoscale latch in a controlled fashion, and sequences of information-transfer operations can be devised to implement arbitrary Boolean logic operations and operators, including NOT, AND, OR, XOR, NOR, NAND, and other such Boolean logic operators and operations, as well as input and output functions. Nanoscale-latch arrays can be combined and interconnected in an almost limitless number of different ways to construct arbitrarily complex, sequential, parallel, or both parallel and sequential computing engines that represent additional embodiments of the present invention.

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