Resources Contact Us Home
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of d

Image Number 13 for United States Patent #7102929.

A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

  Recently Added Patents
Systems, methods, and apparatus to determine physical location and routing within a field of low power beacons
Display control device, display control method, and touchpad input system
Attribute category enhanced search
Lithographic apparatus and device manufacturing method
Contact lens material
Method and system for checking citations
Image processing apparatus and image processing method
  Randomly Featured Patents
Tandem type image forming apparatus
Inflatable laparoscopic retractor
Dipole television antenna
Polyester-amide resin
Methods and apparatus for reading bar code identifications
Wall system and components thereof
Push-pull heterojunction bipolar transistor
Fractal counterpoise, groundplane, loads and resonators
Imaging method of X-ray computerized tomography and apparatus for X-ray computerized tomography
Impulse driving method and apparatus for LCD