Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of d










Image Number 13 for United States Patent #7102929.

A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.








 
 
  Recently Added Patents
Method and apparatus for user selection of advertising combinations
Method and apparatus for analysis of histopathology images and its application to cancer diagnosis and grading
Maize variety hybrid X03A157
Fused thiazole derivatives as kinase inhibitors
Method for testing multi-chip stacked packages
Integrated circuit package system with bonding lands
Modular storage system
  Randomly Featured Patents
LED flashlight with heat-dissipating plate
Process for preparing intermetallic compounds or hydrides thereof
Low profile bicycle pedal and cleat assembly
Method for making electrode
Canopy structure
Dipeptide alkyl esters and their uses
Dredging system and apparatus
Medical injector
Image forming apparatus
Apparatus for use in a pipe bending machine and method for bending pipe