Resources Contact Us Home
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of d

Image Number 13 for United States Patent #7102929.

A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

  Recently Added Patents
Methods and apparatus related to cursor device calibration
Workload interference estimation and performance optimization
Structure and manufacturing method for high resolution camera module
Flavor compound-producing yeast strains
Solid oxide fuel cell having a closed recessed structure
Method and system for performing re-association due to handover in a WLAN mesh network
  Randomly Featured Patents
Communication apparatus and method for a CDMA communication system
Bottle blade
Steering controlling apparatus for trailers
Boot carrier frame
Cellular electrophysiological measurement device and method for manufacturing the same
Foil printing
Optimized call center operations method and system
Oxide cathode
Expansion dowel assembly
Plants and seeds of corn variety CV700979