Resources Contact Us Home
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of d

Image Number 13 for United States Patent #7102929.

A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

  Recently Added Patents
Antenna device and wireless communication apparatus
Housing for gas flow indicator
Dual work function recessed access device and methods of forming
Electrical converter with variable capacitor
High conductive water-based silver ink
Alterable account number
  Randomly Featured Patents
Seam structure of foam sheets for sportswear products
Method and apparatus for forming a cavity in a semiconductor substrate using a charged particle beam
Fire safe seat for a rotary valve
High temperature insulation module
Electric connector permitting testing of electric conductivity of terminals in provisional locking position
Replicated state machine utilizing view change protocol resilient to performance attacks
Zoom lens system
Portable, refrigerant recovery unit
Avoiding optical effects of touch on liquid crystal display
Rotary hearth for calcining kiln