Resources Contact Us Home
Data processing apparatus having memory protection unit

Image Number 7 for United States Patent #7068545.

A data processor (100) has a memory operable to store data values; a memory protection unit (130) operable to associate memory attributes with portions of said memory and to identify a plurality of memory regions corresponding to respective address ranges of said memory. The memory protection unit is operable to associate with at least one of the plurality of memory regions (150) a respective memory region specifier comprising an attributes field (230) for defining a set of memory attributes associated with said memory region and a sub-region field (240) for holding a sub-region membership value. The sub-region membership value specifies, for each of a plurality of sub-regions of the memory region, whether respective sub-regions (160-1 to 160-8) are member sub-regions or non-member sub-regions such that said memory attributes are applied to said member sub-regions but are not applied to said non-member sub-regions.

  Recently Added Patents
Methods and compositions for improving photodynamic therapy through administration of lipids
Automatic logical position adjustment of multiple screens
Control system of substrate processing apparatus, collecting unit, substrate processing apparatus and control method of the substrate processing apparatus
Multi-bank queuing architecture for higher bandwidth on-chip memory buffer
Package for a medicinal product
Dynamic rebasing of persisted time information
Optical writer and image forming apparatus including same
  Randomly Featured Patents
Dye polymers, their preparation and their use in dye compositions
Self centering elevator cable safety brake
Upper stopper device for slide fastener
Synthesis of polysaccharide covered superparamagnetic oxide colloids
Rubber mat for a watercraft
Method to reduce void formation during trapezoidal write pole plating in perpendicular recording
Turbine cooling circuit
Gravity-sensitive locking assembly and weapon container
Thermal processor and components thereof
Reduced transistors data switch port wherein each of a plurality of transmission gates is coupled to both first and second control signals for selectively enabling