Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Directory-based cache coherency scheme for reducing memory bandwidth loss










Image Number 6 for United States Patent #7051166.

A memory system employing a directory-based cache coherency scheme comprises a memory unit, a data bus, a plurality of information buses, and a memory controller. The memory unit comprises a plurality of memory modules storing a plurality of cache lines, with each cache line comprising a plurality of data bits and an associated plurality of informational bits. The data bus is coupled to each of the memory modules and is configured to read/write data from/to the memory modules. One information bus of the plurality of information buses is coupled to each of the memory modules and is configured to read/write informational bits to/from the memory modules.








 
 
  Recently Added Patents
Advanced joint detection in a TD-SCDMA system
Structure of circuit board and method for fabricating the same
Optical imaging device and imaging method for microscopy
High-order harmonic device of cavity filter
Nucleic acid sequences encoding strictosidine synthase proteins
Aperture stop
Cross-linkable compositions
  Randomly Featured Patents
Ionization chamber and mass spectrometry system containing an easily removable and replaceable capillary
Electric air conditioner sustain system
Four wheeled motorcycle
Process for purification of hydrochlorofluoroethanes
Quinolinone compounds as 5-HT.sub.4 receptor agonists
Metalloproteinase inhibitors
Method of producing durable layered coatings
Controlled vortex inducing vascular prosthesis
Device for repositioning ammunition feed of an automatic weapon
Method and apparatus for controlling a provisioning process in a telecommunications system