Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Directory-based cache coherency scheme for reducing memory bandwidth loss










Image Number 3 for United States Patent #7051166.

A memory system employing a directory-based cache coherency scheme comprises a memory unit, a data bus, a plurality of information buses, and a memory controller. The memory unit comprises a plurality of memory modules storing a plurality of cache lines, with each cache line comprising a plurality of data bits and an associated plurality of informational bits. The data bus is coupled to each of the memory modules and is configured to read/write data from/to the memory modules. One information bus of the plurality of information buses is coupled to each of the memory modules and is configured to read/write informational bits to/from the memory modules.








 
 
  Recently Added Patents
Method for forming ventilation holes in an electrode plate
Disk drive
Recording device, recording method, and program
Method and apparatus for linking a web browser link to a promotional offer
System and method for removing oxide from a sensor clip assembly
Vehicle tail lamp
Lentiviral gene transfer vectors and their medicinal applications
  Randomly Featured Patents
Superconductive magnetic resonance magnet without cryogens
Oil supply device for conveyance device
Fluidized bed combustion
Sofa
Method of controlling terminal of MPEG-4 system using caching mechanism
Method of making non-retentive Al-Ni-Co-Fe alloy
Data migration management device and method
Integrated micromachine relay for automated test equipment applications
Interactive inventor's menus within a software computer and video display system
Combination freight and vehicle carrying trailer