Resources Contact Us Home
Dual-trench isolated crosspoint memory array

Image Number 8 for United States Patent #7042066.

A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the n+ Si layer; forming a layer of silicon nitride overlying the p+ layer; forming a top oxide layer overlying the silicon nitride layer; performing a first selective etch of the top oxide layer, the silicon nitride layer, the p+ Si layer, and a portion of the n+ Si layer, to form n+ Si bit lines and bit line trenches between the bit lines; forming an array of metal bottom electrodes overlying a plurality of n-doped silicon (n+ Si) bit lines, with intervening p-doped (p+) Si areas; forming a plurality of word line oxide isolation structures orthogonal to and overlying the n+ Si bit lines, adjacent to the bottom electrodes, and separating the p+ Si areas; forming a plurality of top electrode word lines, orthogonal to the n+ Si bit lines, with an interposing memory resistor material overlying the bottom electrodes; and, forming oxide-filled word line trenches adjacent the word lines.

  Recently Added Patents
Method and system for phase-sensitive magnetic resonance imaging
Virtual image display device and manufacturing method of virtual image display device
Light fixture
Jet pump and reactor
Air filter
Real-time application of filters based on image attributes
Semiconductor device
  Randomly Featured Patents
Fluidic noise suppressor and stabilizer
Dish drying rack for use on a countertop
Magenta development inhibitor releasing coupler
Integrated network communication device
Processing means for use in an optical character recognition system
Resin composition for extrusion molding and extrusion-molded article
Temperature compensated nuclear magnetic resonance apparatus and method
Wired circuit board assembly sheet including striated portions for enhancing rigidity
Method of fabricating acceleration resistant crystal resonators and acceleration resistant crystal resonators so formed
Lacing device for ski boots