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Semiconductor memory device










Image Number 14 for United States Patent #7027342.

In a semiconductor memory device having a crosspoint-type memory cell array, each reference level between two adjacent memory levels when memory levels of multi-level information stored in a memory cell are arranged in order of size of resistance values of a corresponding variable resistive element is defined by a reference current in a middle state between a first and a second current states. In the first current state, a readout current of high resistance selected cell in which the resistance is higher in the two adjacent memory levels becomes the largest state depending on a distribution pattern of a resistance state of the other unselected cell. In the second current state, a readout current of low resistance selected cell in which the resistance is lower in the two adjacent memory levels becomes a smallest state depending on a distribution pattern of a resistance state of the other unselected memory cell.








 
 
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