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Sampling level converter circuit, 2-phase and multiphase expanding circuit, and display device

Image Number 10 for United States Patent #7006068.

A sampling level converter circuit having a fewer number of terminals and reduced power consumption, as well as an expanding circuit having such a sampling level converter circuit. The sampling level converter circuit includes first to third MOS transistors connected serially between a higher-potential power-supply and a lower-potential power-supply, a first capacitor connected to a connection node of the first and second MOS transistors, a fourth MOS transistor connected between an input terminal and the gate terminal of the third MOS transistor and a second capacitor connected to the gate of the third MOS transistor. A sampling pulse signal is supplied to the gates of the first and second MOS transistors, and a signal obtained by inverting this sampling pulse signal is supplied to the gate of the fourth MOS transistor.

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