Resources Contact Us Home
SRAM cell design with high resistor CMOS gate structure for soft error rate improvement

Image Number 6 for United States Patent #6992916.

A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.

  Recently Added Patents
Method for manufacturing iron catalyst
Method for executing an application in a restricted operating environment
Device and method for the removal of a part of a crop
Solution blow spinning
Process for producing thiophene compound and intermediate thereof
Sport tights
Method and system for modeling a bus for a system design incorporating one or more programmable processors
  Randomly Featured Patents
Dental composite resin composition
Collaborative location server/system
Rotary process for forming uniform material
Apparatus for the production of packs, especially cigarette cartons
Arc fault mitigation for photovoltaic systems
Chaining context-sensitive search results
Temporary spinal fixation apparatuses and methods
CMOS image sensor and pixel of the same
Telescoping motorcycle helmet lock
Ear wax guard