Resources Contact Us Home
SRAM cell design with high resistor CMOS gate structure for soft error rate improvement

Image Number 6 for United States Patent #6992916.

A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.

  Recently Added Patents
Compact ion accelerator source
Support member, rotation device comprising such a support and rolling bearing assembly including such a detection device
Single well reservoir characterization apparatus and methods
Noise suppression in speech signals
Semiconductor device having a bonding pad and shield structure of different thickness
Compression molding method and reinforced thermoplastic parts molded thereby
Preservation of liquid foods
  Randomly Featured Patents
Food slicer in the storage position
Vaccine for B-cell malignancies
Variable low-pressure fluid color change cycle
Quick release gauge fitting
Spatial light modulator illumination system
Method of ion implantation
Device and method for reading data stored in a semiconductor device having multilevel memory cells
Infant dressing tray
Method for manufacturing an oxide superconductor device