Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
SRAM cell design with high resistor CMOS gate structure for soft error rate improvement










Image Number 6 for United States Patent #6992916.

A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.








 
 
  Recently Added Patents
Video stabilization
Method and apparatus for editing a program on an optical disc
Cis-alkoxy-substituted spirocyclic 1-H-pyrrolidine-2,4-dione derivatives
(4940
Field emission cathode device and field emission display using the same
Techniques for data assignment from an external distributed file system to a database management system
Stable aqueous composite compositions
  Randomly Featured Patents
Pet food and water dish
Port means for a liquid transport system
Variable drive apparatus
Executing network layered communications of a first system on a second system using a communication bridge transparent to the different communication layers
Thermodynamic amplifier cycle system and method
Urinal
Chart recorder
Transducer with multiple resonant frequencies for an imaging catheter
Architecture and method for remote platform control management
Hybrid sample data filter