Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
SRAM cell design with high resistor CMOS gate structure for soft error rate improvement










Image Number 6 for United States Patent #6992916.

A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.








 
 
  Recently Added Patents
Method and system for constructing a customized web analytics application
Systems and methods for DC-to-DC converter control
Electric rotating machine for vehicle
Chain link
Transmitter having a programmable amplifier operating class
Circuitry for measuring and compensating phase and amplitude differences in NDT/NDI operation
Hepatitis C virus inhibitors
  Randomly Featured Patents
Color measurement instrument
Drum-type motor with inner gear
Photovoltaic element of junction type with an organic semiconductor layer formed of a polysilane compound
Air compressor oil recirculation system
Method and an arrangement for conducting multiple calls simultaneously
Call initiation via calendar
Safety device
Gas sensor for use as a fire detector
Gas riser with free rotating plastic riser casing
Monitoring of retinal temperature during laser therapy