Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
SRAM cell design with high resistor CMOS gate structure for soft error rate improvement










Image Number 5 for United States Patent #6992916.

A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.








 
 
  Recently Added Patents
Methods, systems, and products for providing communications services
Polishing composition
Sample holder and method for treating sample material
Particulate filter with hydrogen sulphide block function
Mobile application for calendar sharing and scheduling
Print system
Obviation of recovery of data store consistency for application I/O errors
  Randomly Featured Patents
Solid-state image pickup apparatus driven at a frequency adaptive to photographic sensitivity
Tooth brush sanitizer
Elevator system
Multiphase induction device
Ejecting liquid using drop charge and mass
Method and system for searching for web content
Disk refiner
Apparatus and method for permeability measurement
Latent heat-ballasted gasifier
Differential protective relay for electrical buses with improved immunity to saturation of current transformers