Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
SRAM cell design with high resistor CMOS gate structure for soft error rate improvement










Image Number 5 for United States Patent #6992916.

A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.








 
 
  Recently Added Patents
Control of an electric machine
Mobility management in a communications system
Organic light emitting display device and method of manufacturing the same
Toner cartridge
Fabrication of thin pellicle beam splitters
Water slide
Strongly bound carbon nanotube arrays directly grown on substrates and methods for production thereof
  Randomly Featured Patents
Telescopic sight having lens holder tube with half socket pivot mount
Snowmobile suspension
Flat input keyboard for data processing machines or the like and process for producing the same
Barrier-free water cooler
Soybean cultivar 96160254
Controller driver and liquid crystal display apparatus using the same
Method and apparatus for electric powered vehicle recharging safety
Semiconductor memory apparatus of which data are accessible by different addressing type
Bonded vehicular glass assemblies utilizing two-component urethanes, and related methods of bonding
Melt blowing apparatus