Resources Contact Us Home
SRAM cell design with high resistor CMOS gate structure for soft error rate improvement

Image Number 5 for United States Patent #6992916.

A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.

  Recently Added Patents
Apparatus and method for manufacturing microneedles
Antisense modulation of C-reactive protein expression
Vehicle exterior
Power management implementation in an optical link
Magnetic memory and method of manufacturing the same
Polypeptides having beta-glucosidase activity and beta-xylosidase activity and polynucleotides encoding same
  Randomly Featured Patents
Preparation of glutaric acid derivatives
Artificial larynx
Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach
Treatment for inflammatory bowel disease with a fibronectin polypeptide
Method and apparatus for packet quarantine processing over a secure connection
Apparatus and method for directional drilling
System for reducing data transmission between coprocessors in a video compression/decompression environment by determining logical data elements of non-zero value and retrieving subset of the
Disinfectant solution bottle
Imidazo[2,1-b]thiazole derivatives
Block management method for flash memory and controller and storage system using the same