Resources Contact Us Home
SDRAM with command decoder coupled to address registers

Image Number 4 for United States Patent #6910096.

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

  Recently Added Patents
Manufacturing aircraft parts
Fast port switching in an audiovisual receiver by use of port pre-authentication by a partial PHY decoder core
Spectral measurement device
Real-image zoom viewfinder and imaging apparatus
Dynamic rebasing of persisted time information
Medicament delivery device and a method of medicament delivery
System and method for confirming delivery of an electronic message
  Randomly Featured Patents
Sulfur removal process
Tape measure that incorporates a marking device
Data recovery using data eye tracking
Micro viscometer
Slave interface circuit for providing communication between a peripheral component interconnect (PCI) domain and an advanced system bus (ASB)
Mine roof supporting system
Suspension arrangement
Fuel and lubricant additives from aminoalkylalkanolamines
Fast trigger ESD device for protection of integrated circuits
Rotating biological contactors for the treatment of waste water