Resources Contact Us Home
SDRAM with command decoder coupled to address registers

Image Number 4 for United States Patent #6910096.

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

  Recently Added Patents
Method and apparatus for secure transfer and playback of multimedia content
Charge pump circuit and power-supply method for dynamically adjusting output voltage
Manufactured product configuration
Cell proliferation inhibitor
Femtocell one-to-many packet delivery
Signal processing apparatus and methods
Chemically bonded carbon nanotube-polymer hybrid and nanocomposite thereof
  Randomly Featured Patents
Process for the preparation of aqueous polyurethane dispersions
Tin oxide, titanium oxide and/or zirconium oxide coated .beta.-eucryptite particles having a negative coefficient of linear thermal expansion and sealing compositions containing said particles
Method for rolling thin metal films
Nerve regeneration chamber
Pinch clip occluder system for infusion sets
Apparatus and method for applying ciphering in universal mobile telecommunications system
Automatic gain control circuit using gain shift
Three dimensional inflatable exhibition product with moving particles inside the exhibition product
Chrysanthemum plant named `Yoseattle`
Word processor work station with a braille reading line