Resources Contact Us Home
SDRAM with command decoder coupled to address registers

Image Number 4 for United States Patent #6910096.

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

  Recently Added Patents
Methods and devices for creating, compressing and searching binary tree
Structure of circuit board and method for fabricating the same
Wine bottle
System and method for redundant array copy removal in a pointer-free language
System and method for displaying relationships between electronically stored information to provide classification suggestions via inclusion
Method for enhanced subsurface electromagnetic sensitivity
  Randomly Featured Patents
Soundboard of composite fibre material construction for acoustic stringed instruments
Female urinary aid device and method of use thereof
Apparatus for casting dental prosthesis
Targeted binding agents directed to uPAR and uses thereof
Network for generating modified microcode addresses
Compensating hitch
Shock absorbing device for hydraulic cylinder
Electrically conductive polymeric
Vertical cavity surface emitting laser including trench and proton implant isolation