Resources Contact Us Home
SDRAM with command decoder coupled to address registers

Image Number 4 for United States Patent #6910096.

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

  Recently Added Patents
Soybean cultivar CL0911444
Making transparent capacitor with multi-layer grid
Electrical installation arrangement
Vapor phase decarbonylation process
Identifying users of remote sessions
Prevention and treatment of oxidative stress disorders by gluthathione and phase II detoxification enzymes
Cancer treatment kits comprising therapeutic antibody conjugates that bind to aminophospholipids
  Randomly Featured Patents
Efficient intrusion detection
Fluid dispensing device
Resin composition and molded article thereof
Ratchet wrench
Method of forming a self-gated transistor and structure therefor
Assembly and method for head-up display (HUD) tray harmonization
System and method for using a force model to control process configurations for the encapsulation of a web
Torsional vibration damper having helical torsion springs
Lobster trap with ring guard assembly
Disperse dyes which are convertible into a thermomigration fast form