Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
SDRAM with command decoder coupled to address registers










Image Number 4 for United States Patent #6910096.

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).








 
 
  Recently Added Patents
Churn prediction and management system
Wafer level package and fabrication method
Enhanced telephony services
Transfer device and image forming apparatus including regulation member
Low-complexity motion vector prediction systems and methods
Portable device for treating insect bites and the like
Method and apparatus for allocating erasure coded data to disk storage
  Randomly Featured Patents
Arrow head
Polyglycolic acid resin particle composition and process for production thereof
Electronic magnetic compass system
Photon counting imaging detector system
Sander
Signature feeding and stitching apparatus
Liquid crystal display screen
MOS transistor output circuit
Method and system for directing a wireless user to a location for improved communication
Credit card