Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
SDRAM with command decoder coupled to address registers










Image Number 4 for United States Patent #6910096.

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).








 
 
  Recently Added Patents
Surface modification
Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
Image generation based on a plurality of overlapped swathes
Method of operating an election ballot printing system
Vertical gate LDMOS device
Enterprise seamless mobility
System and method for routing streaming data requests
  Randomly Featured Patents
Blister packaging
Winding/rewinding apparatus and method for a camera
Alkali-free aluminoborosilicate glasses for lighting means with external or internal contacting
Circuit arrangement for profiling a programmable processor connected via a uni-directional bus
Portable telephony apparatus with music tone generator
Ultrasound system for cerebral blood flow monitoring
Substrate support of integral construction
Signal-input device
Autoinjector
Vacuum rotary dryer