Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
SDRAM with command decoder coupled to address registers










Image Number 4 for United States Patent #6910096.

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).








 
 
  Recently Added Patents
Method and apparatus for bearing thrust monitoring
Boundary scan chain for stacked memory
Techniques for management of shared resources in wireless multi-communication devices
Connector
Method and apparatus for providing a content control signal in a media player via color burst phase modifications
System for executing 3D propagation for depth image-based rendering
Method and system for automatically updating a software QA test repository
  Randomly Featured Patents
Station protector for communications lines
Thermal insulator
Negative-acting no-process printing plates
Hair cosmetic compositions
Laser diffraction particle sizing method using a monomode optical fiber
Electrofusion joint and hot water supply header using the same
Copy sheet stack apparatus
Tissue penetration device
Aerial day/night refueling stations
In-plane switching mode liquid crystal display with a retardation layer formed directly on a color filter substrate in a reflection region