Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
SDRAM with command decoder coupled to address registers










Image Number 4 for United States Patent #6910096.

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).








 
 
  Recently Added Patents
Powerline communication device with load characterization functionality
Lighting fixture
Redundant parallel operation of motor vehicle electrical system generators
Flame-proofed thermoplastic compositions
Method of synchronization for low power idle
Resist composition and method for producing resist pattern
Generating wiki pages from content and transformation objects
  Randomly Featured Patents
Electrical connector with position assurance and double lock
Voltage-mode driver with pre-emphasis
Cloned cell line expressing rat .beta..sub.3A adrenergic receptor
Pen with stylus tip
Ceramic-metal laminate
Semiconductor structure
Operating table with a patient support surface tiltable around the longitudinal and transverse axes
Monolithic micro scanning device
Method of manufacturing a buried-channel charge-coupled image sensor
Snubber circuit and power transformer using the same