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Threshold voltage adjustment method of non-volatile semiconductor memory device and non-volatile semiconductor memory device










Image Number 6 for United States Patent #6879521.

It is intended to provide a nonvolatile semiconductor memory device which maintains the maximum number of over-erase memory cells which are conductive when adjusting the threshold voltage after data erase by controlling the gate voltage of a memory cell continuously in order to adjust the threshold voltage in a short time and a nonvolatile voltage adjustment method. There is formed a feedback loop for controlling the number of memory cells to be conductive in a memory cell group by controlling a gate voltage generating circuit through a differential amplifier from a drain terminal and the gate voltage generating circuit is controlled by the differential amplifier so as to maintain the drain voltage at a predetermined drain voltage VRF. A variable gate voltage can be controlled continuously by a feedback loop for controlling the variable gate voltage based on a difference voltage between the drain voltage and the predetermined drain voltage. Thus, effective threshold voltage adjustment operation is enabled corresponding to a current supply capacity regardless of the current supply capacity of the drain voltage generating circuit.








 
 
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