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Selective polysilicon stud growth

Image Number 6 for United States Patent #6861691.

A memory cell includes a bit line contact feature that is characterized by a contact hole bounded by insulating side walls including first and second pairs of opposing insulating side walls. The first pair of opposing insulating side walls comprises respective layers of insulating spacer material formed over a conductive line. The second pair of opposing insulating side walls comprises respective layers of insulating material formed between respective contact holes. The contact hole is filled to an uppermost extent of the insulating side walls with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile. The contact hole may define either a bitline contact or a storage node contact.

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