Resources Contact Us Home
Selective polysilicon stud growth

Image Number 6 for United States Patent #6861691.

A memory cell includes a bit line contact feature that is characterized by a contact hole bounded by insulating side walls including first and second pairs of opposing insulating side walls. The first pair of opposing insulating side walls comprises respective layers of insulating spacer material formed over a conductive line. The second pair of opposing insulating side walls comprises respective layers of insulating material formed between respective contact holes. The contact hole is filled to an uppermost extent of the insulating side walls with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile. The contact hole may define either a bitline contact or a storage node contact.

  Recently Added Patents
Key management using quasi out of band authentication architecture
Method and apparatus for controlling the use of data stored on a media sample
Method and device for authenticating transmitted user data
Reference circuit with curvature correction using additional complementary to temperature component
SMS transport resource control
Image forming apparatus detecting color patterns and generating interleaf images at predetermined position
Monitoring device for monitoring a display device
  Randomly Featured Patents
Valve manifold stacking base
Process for producing a methyl methacrylate-based resin article
Spinning top
Key input indicating tone generating apparatus for small-sized electronic devices
Stump grinder apparatus
Lift apparatus
Carboxyalkylacylamino acids
Dining chair
Fire alarm system
Solvent solutions of siloxane fluids