Resources Contact Us Home
Selective polysilicon stud growth

Image Number 6 for United States Patent #6861691.

A memory cell includes a bit line contact feature that is characterized by a contact hole bounded by insulating side walls including first and second pairs of opposing insulating side walls. The first pair of opposing insulating side walls comprises respective layers of insulating spacer material formed over a conductive line. The second pair of opposing insulating side walls comprises respective layers of insulating material formed between respective contact holes. The contact hole is filled to an uppermost extent of the insulating side walls with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile. The contact hole may define either a bitline contact or a storage node contact.

  Recently Added Patents
Chemically bonded carbon nanotube-polymer hybrid and nanocomposite thereof
Elastic wave device having a capacitive electrode on the piezoelectric substrate
Developing device
Reframing circuitry with virtual container drop and insert functionality to support circuit emulation protocols
Transparent conductive structure
Semiconductor device comprising a Fin and method for manufacturing the same
  Randomly Featured Patents
Silicon-containing material having at least one densification aid including alumina
Electrical connector endbell
Retractable safety barrier
Intravascular ultrasound transducer assembly having a flexible substrate and method for manufacturing such assembly
Laundering apparatus, method of operating a laundry machine, control system for an electronically commutated motor and method of operating an electronically commutated motor
Pneumatic shock absorber with rolling bellows
System for disconnecting an electrical power source from a load
Process for profiling bristle fields
Chaise longue
Nanocrystalline heterojunction materials