Resources Contact Us Home
Selective polysilicon stud growth

Image Number 6 for United States Patent #6861691.

A memory cell includes a bit line contact feature that is characterized by a contact hole bounded by insulating side walls including first and second pairs of opposing insulating side walls. The first pair of opposing insulating side walls comprises respective layers of insulating spacer material formed over a conductive line. The second pair of opposing insulating side walls comprises respective layers of insulating material formed between respective contact holes. The contact hole is filled to an uppermost extent of the insulating side walls with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile. The contact hole may define either a bitline contact or a storage node contact.

  Recently Added Patents
Automated pizza preparation and vending system
Control method of LPI lamp for LPI vehicle and logic therefor
TPO compositions, articles, and methods of making the same
Terminal device and image printing method
Aromatic amine derivative, organic electroluminescent element employing the same, and process for producing aromatic amine derivative
Telecommunications system and method
System and method for the heterologous expression of polyketide synthase gene clusters
  Randomly Featured Patents
Measuring the velocity of small moving objects such as cells
Melt and hold furnace for non-ferrous metals
Nail file
Card edge connector
One step molded all plastic boat and manufacture of the same
Random access valve
Squeegee for surface cleaning
Control panel of chassis for a video game console
Cationic coating compositions for electrodeposition over rough steel