Resources Contact Us Home
Flash memory having improved core field isolation in select gate regions

Image Number 4 for United States Patent #6815292.

A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.

  Recently Added Patents
Uni-directional transient voltage suppressor (TVS)
Prompt gap varying optical filter, analytical instrument, optical device, and characteristic measurement method
SRB enhancement on HS-DSCH during cell change
Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture
Particulate filter with hydrogen sulphide block function
Adjusting dental prostheses based on soft tissue
  Randomly Featured Patents
Spectrally coordinated pattern search-imaging system and method
Apparatus and methods for systematic non-uniformity correction using a gas cluster ion beam
Method of printing a composite image of human figure and personal data using CRT
Os calsis prosthesis
Appliance mounting device
Therapeutic arthritis glove with expandable gold rings
Method to improve performance of secondary active components in an esige CMOS technology
Storage and display rack for recorded media
Apparatus for sizing a femoral component
Transvaginal suturing system