Resources Contact Us Home
Flash memory having improved core field isolation in select gate regions

Image Number 4 for United States Patent #6815292.

A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.

  Recently Added Patents
Secure provisioning of a portable device using a representation of a key
Doherty amplifier circuit
System or method to assist and automate an information security classification and marking process for government and non-government organizations for information of an electronic document
Method and device for determining processed image data about a surround field of a vehicle
Electronic device with multi-orientation
Utility knife
  Randomly Featured Patents
System for completing water injector wells
Motor vehicle and toy replica thereof
Promoters and gene expression method by using the promoters
Electrode structure for high temperature heated body
Motor field assembly
Hair iron
Dynamically determining a buffer-stack overrun
Precursors of 3-alkoxyalkanols and processes for the preparation of 3-alkoxyalkanols
Metal radionuclide chelating compounds for improved chelation kinetics
Treatment of obesity