Resources Contact Us Home
Synchronous semiconductor memory device

Image Number 18 for United States Patent #6731559.

A synchronous semiconductor memory device has a memory section which includes a memory cell array having a plurality of memory cells and which is capable of a read operation of reading information from the memory cells according to a read command and a write operation of writing information into the memory cells according to a write command. The synchronous semiconductor memory device further has a command sensing circuit which senses whether a first command inputted in synchronization with an external clock signal is the read command or the write command. The synchronous semiconductor memory device further has a bank timer circuit which, when the command sensing circuit has sensed either the read command or the write command, sets the end time of the restore operation of a row address strobe (RAS) and the start time of the precharge operation of the RAS according to the external clock signal.

  Recently Added Patents
Liquid crystal display backlight control
Semiconductor light-receiving device
Memory elements with increased write margin and soft error upset immunity
Local call local switching at handover
Valved, microwell cell-culture device and method
Interlock apparatus for vacuum circuit breaker
Image forming apparatus
  Randomly Featured Patents
User interface having a carousel view for representing structured data
Image forming apparatus, control method therefor, and storage medium storing control program therefor
Dispersion for preventing electrification antistatic film and image display device
Apparatus and method for polishing a fiber optic connector
Method for repairing partitions of a turbine diaphragm
Device for energy transmission for mechanical control, in particular for the control of braking pressure in a brake
High frequency module
Wallpaper applicator
Radio-frequency IC for a mobile radio transmitter